The invention relates to a phase detector, more particularly, a frequency phase detector for differentiating frequencies having small phase differences, and generating a pulse in response to a first frequency leading a second frequency, the pulses driving a charge pump used in one of a phase-locked loop and a delay-locked loop.
Operating speeds of microprocessors and other digital systems are increasing in frequencies. At higher frequencies the timing delays and other uncertainties associated with the clock signal generation and distribution in a system are critical factors in a systems overall performance and reliability. System performance is optimized by carefully considering the attributes of the components used in designing the clock circuit, an important component in any synchronous digital system. A clock circuit includes clock generation and clock distribution. Clock generation takes the output of some oscillator source and manipulates it to obtain pulses with a specific frequency, duty cycle, and amplitude. These signals are then fanned out to various system components by a clock distribution network. As system speeds rise, the uncertainties of meeting setup, hold, and pulse duration requirements become critical due to a narrowing time window. Therefore, each component of a clocking circuit must be carefully designed and be high performance.
Phase-locked loop (PLL) and delay-locked loop (DLL) circuits are often used in clocking circuits. A conventional PLL, shown in FIG. 1, consists of five components including phase detector 4, charge pump 6, low pass filter 8, voltage controlled oscillator 10, and programmable frequency divider 12. As shown, phase detector 4 includes an input for receiving reference frequency 14 and a second input for receiving variable frequency 18. Phase detector 4 generates a phase difference between reference frequency 14 and variable frequency 18. The phase difference is used as an input to charge pump 6 which generates a variable voltage. The voltage passes through low pass filter 8 to remove noise and is used as an input to voltage controlled oscillator 10 to vary the frequency. A feedback loop extends from voltage controlled oscillator 10 to programmable frequency divider 12 to phase detector 4. Programmable frequency divider 12 divides the frequency from voltage controlled oscillator 10 by hundreds or thousands of numerical values, as selected.
A traditional CMOS implementation of a phase detector, consisting of two flip flops, is shown in FIG. 2. The traditional phase detector often includes a logic NAND gate and when both inputs to the logic NAND gate are high, then the flip flop reset signal is activated, bringing the flip flop output to ground. A RS latch is also used as part of a phase detector circuit.